A scheme in which a packaging process (post-process) and a wafer process (pre-process) are integrated to each other to complete a packaging step in a wafer state, i.e., a technique so-called a wafer level CSP has the following advantage. That is, since a packaging process is performed by applying a wafer process, the number of steps can be made considerably smaller than that of a conventional method in which a packaging process (post-process) is performed to each chip cut from a wafer. The wafer level CSP is also called a wafer process package (WPP).
In the wafer level CSP, a wiring layer in the CSP called an interposer for converting the pitch of bonding pads into the pitch of solder bumps can be replaced with rerouting layers formed on a wafer. For this reason, the wafer level CSP is expected to achieve the reduction in number of steps and a reduction in manufacturing cost of a CSP.
The wafer level CSP is described in, e.g., “Electronics Mount Technology extra edition 2000” issued by Gijyutsu-chyosa-kai Corporation (issued on 28th May, 2000) pp. 81 to 113, International Patent Publication No. WO99/23696, and the like.
In a conventional method in which a package process (post-process is performed to each chip cut from a wafer, in order to rapidly cope with a demand of a client, in, e.g., a memory LSI (DRAM: Dynamic Random Access Memory), operation modes such as word configurations and bit configurations are changed (product type switching) by a bonding option. As a technique which performs a change of electric characteristics for respective divided chips, i.e., a bonding option, techniques described in Japanese Patent Application Laid-Open No. 11-40563 and Japanese Patent Application Laid-Open No. 7-161761 are known.
In Japanese Patent Application Laid-Open No. 11-40563 of these publications, the three following methods are described. That is, (1) two wirings having different electric characteristics are formed to be connected to bonding pads (semiconductor element electrodes arranged on a semiconductor chip) to which bonding wires, tape leads, or external connection balls are connected, and any one of the wirings is cut by a laser depending on required electric characteristics, (2) nodes of bonding wires which connect semiconductor element electrodes (bonding pads) arranged on a semiconductor chip and electrode portions of a semiconductor package to each other are changed, and (3) arrangement positions of external connection balls connected to electrodes (bonding pads) of a semiconductor chip are changed in a CSP.
Japanese Patent Application Laid-Open No. 7-161761 describes the following method. That is, in a semiconductor device in which bonding pads on the surface of a semiconductor element are connected to a plurality of leads with bonding wires, plural lines of pad groups each constituted by arranging a plurality of bonding pads having the same function in a line are arranged at the central portion of the semiconductor element, and bonding pads to which the bonding wires are connected are changed, so that connection relations between the leads and the bonding pads are changed depending on product types.